In a conventional method of logic circuit verification, there are several types of logic circuit verification. One type is a logic simulation tool (as disclosed in Official gazette of JP-A No. 151297/1993 (pages 2 and 3, FIG. 1)), which is a dynamic verification tool and a second type is a property verification tool (as disclosed in Official gazette of JP-A No. 196342/2003 (pages 6 and 7, FIG. 1)), which is a static verification tool.
The logic simulation tool simulates an operation for each compiled RTL (Register Transfer Level) description by setting a test pattern and verifying whether or not signals are output as designed with respect to the test pattern.
The property verification tool uses Boolean algebra or the like to determine whether or not each logic circuit is described in accordance with the property (design specification), thereby verifying whether or not the logic circuit satisfies the property.
Logic circuit designers use a hardware description language (HDL) such as the VHDL (VHDIC Hardware Description Language), the Verilog-HDL language, or the like, or a programming language such as the C language, the Java® language, or the like to describe circuit operations. The logic simulation tool and the property verification tool are operated to verify whether or not the contents are described as the circuit operations are designed.